TMPR3911 datasheet(189/462 Pages) TOSHIBA

189 / 462 page

Chapter 7 CHI Module

7-15

7.4

CHI Registers

7.4.1

CHI Control Register

OFFSET

= $1D8:

Bit

Label

RESET

Read/Write

31-30

Reserved

CHILOOP

R/W

CHIENTEST

R/W

CHIFSDIR

R/W

26-25

CHIFSWIDTH[1:0]

R/W

24-20

CHINCHAN[4:0]

R/W

19-16

CHITXBOFF[3:0]

R/W

15-12

CHIRXBOFF[3:0]

R/W

TXMSBFIRST

R/W

RXMSBFIRST

R/W

CHIRXFSPOL

R/W

CHITXFSPOL

R/W

7CHIRXEDGE

R/W

6CHITXEDGE

R/W

5CHIFSEDGE

R/W

CHITXFSEDGE

R/W

CHICLK2XMODE

R/W

2CHIRXEN

R/W

1CHITXEN

R/W

ENCHI

R/W

CHILOOP:

This bit is used for IC testing and should not be set. Setting this bit to a logic “1” will cause the

CHI serial transmitted data to be internally looped back to the CHI serial receive data path. The

data is inverted when this mode is selected. Clearing this bit to a logic “0” selects the normal

CHIDIN pin as the CHI serial receive data source.

CHIENTEST:

This bit is used for IC testing and should not be set.

CHIFSDIR:

This bit controls the direction of the CHIFS pin. Setting this bit to a logic “1” configures CHIFS

to be an output (CHI sync master mode). Clearing this bit to a logic “0” configures CHIFS to be an

input (CHI sync slave mode). Note that CHIRXFSPOL and CHIFSEDGE bits must be set to

proper values even when CHIFSDIR is set to a logic “1” (CHI sync master mode).

TMPR3911 Datasheet(PDF) 189 Page - Toshiba Semiconductor

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