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ADS5295IPFP Datasheet(PDF) 27 Page - Texas Instruments

Part # ADS5295IPFP
Description  12-Bit, 100-MSPS, 8-Channel Analog-to-Digital Converter
PDF  93 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADS5295IPFP Datasheet(HTML) 27 Page - Texas Instruments

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Register Address
Register Data
SDATA
SCLK
CS
t
SLOADS
t
SLOADH
t
SCLK
t
DSU
t
DH
RESET
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ADS5295
www.ti.com
SBAS595 – DECEMBER 2012
DEVICE CONFIGURATION
SERIAL INTERFACE
The ADC has a set of internal registers that can be accessed by the serial interface formed by the CS (serial
interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serially shifting bits into
the device is enabled when CS is low. The serial data (on the SDATA pin) are latched at every SCLK falling
edge when CS is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when
CS is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded
in multiples of 24-bit words within a single active CS pulse. The first eight bits form the register address and the
remaining 16 bits are the register data. The interface can function with SCLK frequencies from 15 MHz down to
very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to default values. This initialization can be accomplished
in one of two ways:
1. Either through a hardware reset by applying a high pulse on the RESET pin (of widths greater than 10 ns),
as shown in Figure 43; or
2. By applying a software reset. When using the serial interface, set the RESET bit (register 00h, bit D7) high.
This setting initializes the internal registers to default values and then self-resets the RESET bit low. In this
case, the RESET pin is kept low (inactive).
Figure 43. Serial Interface Timing Diagram
Table 5. Timing Characteristics for Figure 43(1)
PARAMETER
MIN
TYP
MAX
UNIT
fSCLK
SCLK frequency (equal to 1 / tSCLK)
>dc
15
MHz
tSLOADS
CS to SCLK setup time
33
ns
tSLOADH
SCLK to CS hold time
33
ns
tDSU
SDATA setup time
33
ns
tDH
SDATA hold time
33
ns
(1)
Typical values are at TA = +25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX =
+85°C, unless otherwise noted.
Copyright © 2012, Texas Instruments Incorporated
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