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ADS5295IPFP Datasheet(PDF) 48 Page - Texas Instruments |
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ADS5295IPFP Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 93 page  ADS5295 SBAS595 – DECEMBER 2012 www.ti.com Register 42h D15 D14 D13 D12 D11 D10 D9 D8 EN_PHASE_ 0 0 0 0 0 0 0 DDR D7 D6 D5 D4 D3 D2 D1 D0 0 PHASE_DDR1 PHASE_DDR0 0 0 0 0 0 Bit D15 This bit enables LCLK phase programmability. Bits D[14:7] Must write '0' Bits D[6:5] PHASE_DDR[1:0] These bits control the LCLK output phase relative to data. Refer to the Programmable LCLK Phase section. Bits D[4:0] Must write '0' Register 45h D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 PAT_DESKEW_SYNC[1:0] Bits D[15:2] Must write '0' Bit D1 PAT_DESKEW_SYNC1 0 = Inactive 1 = Sync pattern mode enabled; ensure that D0 is '0' Bit D0 PAT_DESKEW_SYNC0 0 = Inactive 1 = Deskew pattern mode enabled; ensure that D1 is '0' 48 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS5295 |
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