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ADS5295IPFP Datasheet(PDF) 75 Page - Texas Instruments

Part # ADS5295IPFP
Description  12-Bit, 100-MSPS, 8-Channel Analog-to-Digital Converter
PDF  93 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADS5295IPFP Datasheet(HTML) 75 Page - Texas Instruments

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ADS5295
www.ti.com
SBAS595 – DECEMBER 2012
DIGITAL OUTPUT INTERFACE
SERIAL LVDS INTERFACE
The ADS5295 offers several flexible output options, making the device easy to interface to an application-specific
integrated circuit (ASIC) or a field-programmable gate array (FPGA). Each option can be easily programmed
using the serial interface. A summary of all available options is listed in Table 20 along with the default values
after power-up and reset. Following Table 20, each option is described in detail. Table 21 lists the two-wire
register settings for the LVDS interface.
Table 20. Summary of Output Interface Options
AVAILABLE IN:
DEFAULT AFTER
ONE-
TWO-
POWER-UP AND
FEATURE
OPTIONS
WIRE
WIRE
RESET
BRIEF DESCRIPTION
One-wire: ADC data are sent serially over one pair
of LVDS pins.
Wire interface
One- and two-wire
N
N
One-wire
Two-wire: ADC data are split and sent serially over
two pairs of LVDS pins.
12x
Y
Y
12x
10x
Y
Y
12x
To be used with digital processing functions, such
Serialization factor
14x
Y
Y
as averaging and decimation filers.
To be used with digital processing functions, such
16x
Y
N
as averaging and decimation filers.
Only available with one-wire interface for 12x, 10x,
6x, 5x, 7x, 8x
Y
N
6x
14x, and 16x serialization factors, respectively.
DDR bit clock frequency
Only available with two-wire interface for 12x, 10x,
3x, 2.5x, 3.5x, 4x
N
Y
6x
14x, and 16x serialization factors, respectively.
1x sample rate
Y
N
1x
Frame clock frequency
1/2x sample rate
N
Y
1x
Only available with the two-wire interface.
Byte-wise
N
Y
Byte-wise
Byte-wise: the ADC data are split into upper and
lower bytes that are output on separate wires.
Only available with the two-wire interface.
Bit sequence
Bit-wise
N
Y
Byte-wise
Bit-wise: the ADC data are split into even and odd
bits that are output on separate wires.
Only available with the two-wire interface.
Word-wise
N
Y
Byte-wise
Word-wise: successive ADC data samples are sent
over separate wires.
Table 21. Register Settings for Two-wire LVDS Interface
D[7:0]
D15 (EN_WORD_BIT_WISE)
D8 (EN_BIT_WISE)
LVDS OUTPUT
(EN_WORDWISE_BY_CH)
0
X
X
Byte-wise mode
1
X
1
Word-wise mode
1
1
0
Bit-wise mode
Copyright © 2012, Texas Instruments Incorporated
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