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ADS5295IPFP Datasheet(PDF) 80 Page - Texas Instruments |
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ADS5295IPFP Datasheet(HTML) 80 Page - Texas Instruments |
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80 / 93 page  PHASE_DDR[1:0] = 00 ADCLKP LCLKP DATA OUT PHASE_DDR[1:0] = 11 ADCLKP LCLKP DATA OUT ADCLKP LCLKP DATA OUT PHASE_DDR[1:0] = 01 ADCLKP LCLKP DATA OUT PHASE_DDR[1:0] = 10 PHASE_DDR[1:0] = 10 ADCLKP LCLKP DATA OUT ADS5295 SBAS595 – DECEMBER 2012 www.ti.com PROGRAMMABLE LCLK PHASE The ADS5295 enables the edge of the output bit clock (LCLK) to be programmed with the PHASE_DDR register bits. The default value of PHASE_DDR after reset is '10'. The default phase is shown in Figure 72. Figure 72. Default LCLK Phase The phase can also be changed by changing the value of the PHASE_DDR[1:0] bits, as shown in Figure 73. Figure 73. Programmable LCLK Phases 80 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS5295 |
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