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ADS5295IPFP Datasheet(PDF) 57 Page - Texas Instruments |
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ADS5295IPFP Datasheet(HTML) 57 Page - Texas Instruments |
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57 / 93 page  ADS5295 www.ti.com SBAS595 – DECEMBER 2012 Register BEh D15 D14 D13 D12 D11 D10 D9 D8 EN_LVDS_ 0 0 0 0 0 DELAY_DATA_R[1:0] PROG D7 D6 D5 D4 D3 D2 D1 D0 DELAY_LCLK_R[2:0] DELAY_DATA_F[1:0] DELAY_LCLK_F[2:0] Bit D15 This bit enables LVDS edge delay programmability. Bits D[14:10] Must write '0' Bits D[9:8] Refer Table 22 for settings. Bits D[7:5] Refer Table 23 for settings. Bits D[4:3] Refer Table 22 for settings. Bits D[2:0] Refer Table 23 for settings. Register F0h D15 D14 D13 D12 D11 D10 D9 D8 EN_EXT_REF 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 The EN_HIGH_ADDRS register bit (register 01h, bit D4) must be set to '1' to allow access to this register. Bit D15 EN_EXT_REF 0 = Internal reference mode (default) 1 = External reference mode enabled; apply the reference voltages on the REFT and REFB pins Bits D[14:0] Must write '0' Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 57 Product Folder Links: ADS5295 |
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