ADS5295IPFP datasheet(76/93 Pages) TI2

76 / 93 page

Frame Clock

(ADCLK Frequency = 1x fS)

Input Clock

(CLK Frequency = fS)

Sample N+1

(D0)

(D1)

(D2)

(D3)

(D4)

(D5)

(D6)

(D7)

(D8)

(D9)

(D0)

(D1)

(D2)

Bit Clock

(LCLK Frequency = 5x fS)

Output Data

(1)

(OUTA Data rate = 10x fS)

Sample N

Frame Clock

(ADCLK Frequency = 1x fS)

Input Clock

(CLK Frequency = fS)

Sample N+1

D11

(D0)

D10

(D1)

(D2)

(D3)

(D4)

(D5)

(D6)

(D7)

(D8)

(D9)

(D10)

(D11)

D11

(D0)

D10

(D1)

Bit Clock

(LCLK Frequency = 6x fS)

Output Data

(1)

(OUTA Data rate = 12x fS)

Sample N

ADS5295

SBAS595 – DECEMBER 2012

www.ti.com

One-Wire, 12x Serialization with DDR Bit Clock and 1x Frame Clock

The 12-bit ADC data are serialized and output over one LVDS pair per channel along with a 6x bit clock and a 1x

frame clock, as shown in Figure 67. The output data rate is a 12x sample rate; therefore, it is suited for low

sample rates.

(1) The upper data bit is the MSB-first mode data bit and the lower data bit is the LSB-first mode data bit.

Figure 67. LVDS Output Interface Timing Diagram (One-Wire, 12x Serialization)

One-Wire, 10x Serialization with DDR Bit Clock and 1x Frame Clock

The 10 upper bits of the 12-bit ADC data are serialized and output over one LVDS pair per channel along with a

5x bit clock and a 1x frame clock, as shown in Figure 68. The output data rate is a 10x sample rate; therefore, it

is suited for low sample rates, typically up to 65 MSPS.

(1) The upper data bit is the MSB-first mode data bit and the lower data bit is the LSB-first mode data bit.

Figure 68. LVDS Output Interface Timing Diagram (One-Wire, 10x Serialization)

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