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ADS5295IPFP Datasheet(PDF) 28 Page - Texas Instruments |
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ADS5295IPFP Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 93 page  SEN t 1 t 2 t 3 Power Supply AVDD, LVDD RESET ADS5295 SBAS595 – DECEMBER 2012 www.ti.com Reset Timing Figure 44 shows a timing diagram for the reset function. Figure 44. Reset Timing Diagram Table 6. Timing Characteristics for Figure 44(1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Delay from AVDD and LVDD power-up t1 Power-on delay 1 ms to active RESET pulse t2 Reset pulse width Pulse width of active RESET signal 50 ns t3 Register write delay Delay from RESET disable to CS active 100 ns (1) Typical values are at TA = +25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, unless otherwise noted. (2) A high pulse on the RESET pin is required when initialization is done via a hardware reset. 28 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS5295 |
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