ADS5295IPFP datasheet(35/93 Pages) TI2

35 / 93 page

ADS5295

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SBAS595 – DECEMBER 2012

D15

D14

D13

D12

D11

D10

TP_HARD_

PRBS_SEED_

PRBS_

TP_SOFT_

PRBS_TP_EN

SYNC

FROM_REG

MODE_2

SYNC

TEST_PATT[2:0]

BITS_CUSTOM2[11:10]

BITS_CUSTOM1[11:10]

All bits default to '0' after reset.

Bit D15

TP_HARD_SYNC

0 = Inactive

1 = The external SYNC feature is enabled for syncing test patterns

Bit D14

PRBS_SEED_FROM_REG

0 = Disabled

1 = The PRBS seed is now able to be chosen from registers 23h and 24h

Bit D13

PRBS_MODE_2

The PRBS 9-bit LFSR (23-bit LFSR) is the default mode.

Bit D12

PRBS_TP_EN

0 = PRBS test pattern disabled

1 = PRBS test pattern enabled

Bits D[11:9]

Must write '0'

Bit D8

TP_SOFT_SYNC

0 = No sync

1 = Software sync bit for the test patterns on all eight channels

Bit D7

Must write '0'

Bit D6

TEST_PATT2

0 = Normal operation

1 = A repeating full-scale ramp pattern is enabled on the outputs; ensure that bits D4 and

D5 are '0'

Bit D5

TEST_PATT1

0 = Normal operation

1 = Enables a mode where the output toggles between two defined codes; ensure that bits

D4 and D6 are '0'

Bit D4

TEST_PATT0

0 = Normal operation

1 = Enables a mode where the output is a constant specified code; ensure that bits D5 and

D6 are '0'

Bits D[3:2]

BITS_CUSTOM2[11:10]

These bits are the two MSBs for the second code of the dual custom patterns.

Bits D[1:0]

BITS_CUSTOM1[11:10]

These bits are the two MSBs for the single custom pattern (and for the first code of the dual

custom patterns).

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