ADS5295IPFP datasheet(60/93 Pages) TI2

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CLKP

CLKN

CMOS

Clock Input

0.1 F

CLKP

CLKN

TERM

Differential

LVDS

Clock Input

0.1 F

CLKP

CLKN

TERM

Differential

LVPECL

Clock Input

TERM

CLKP

CLKN

0.1 F

Differential

Sine-Wave

Clock Input

ADS5295

SBAS595 – DECEMBER 2012

www.ti.com

CLOCK INPUT

The ADS5295 can operate with both single-ended (CMOS) and differential input clocks (such as sine wave,

LVPECL, and LVDS). Operating with a low-jitter differential clock is recommended for good SNR performance,

especially at input frequencies greater than 30 MHz. In the differential mode, the clock inputs are internally

biased to a 0.95-V common-mode voltage. While driving with an external LVPECL or LVDS driver, TI

recommends ac-coupling the clock signals so that the clock pins are correctly biased to the common-mode

voltage (0.95 V). To operate using a single-ended clock, connect a CMOS clock source to CLKP and tie CLKN to

GND. The device automatically detects the presence of a single-ended clock without requiring any configuration

and disables the internal biasing. Typical clock termination schemes are shown in Figure 51, Figure 52,

Figure 53, and Figure 54.

Figure 51. Differential Sine-Wave Clock Driving

Figure 52. Differential LVPECL Clock Driving

Circuit

Figure 53. Differential LVDS Clock Driving Circuit

Figure 54. Single-Ended Clock Driving Circuit

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ADS5295IPFP Datasheet(PDF) 60 Page - Texas Instruments

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