ADS5295IPFP datasheet(81/93 Pages) TI2

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tDR

tCR

tDF

DATA

LCLKN

LCLKP

tCF

ADS5295

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SBAS595 – DECEMBER 2012

PROGRAMMABLE LVDS OUTPUT CLOCK AND DATA EDGES

The ADS5295 enables the edges of the output data and output bit clock to be programmed with the

DELAY_DATA and DELAY_LCLK register bits.

Figure 74 details the timing of the output data and clock edge movements.Table 22 and Table 23 show the

Figure 74. LVDS Interface Output Data and Clock Edge Movement

Table 22. LVDS Interface Output Data Delay Settings(1)

DATA DELAY, RISING CLOCK

DATA DELAY, FALLING CLOCK

EDGE

DELAY_DATA_R[1:0]

tDR, Typical (ps)

DELAY_DATA_F[1:0]

tDF, Typical (ps)

120

(1)

Delay settings are the same for both 10x and 12x serialization modes.

Table 23. LVDS Interface Output Clock Delay Settings(1)

CLOCK RISING EDGE DELAY

CLOCK FALLING EDGE DELAY

DELAY_LCLK_R[2:0]

tCR, Typical (ps)

DELAY_LCLK_F[2:0]

tCF, Typical (ps)

120

106

159

202

244

(1)

Delay settings are the same for both 10x and 12x serialization modes.

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