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MP8796B Datasheet(PDF) 45 Page - Monolithic Power Systems |
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MP8796B Datasheet(HTML) 45 Page - Monolithic Power Systems |
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45 / 52 page ![]() MP8796B – 16V, 30A, SYNCHRONOUS STEP-DOWN CONVERTER WITH PMBUS MP8796B Rev. 1.0 www.MonolithicPower.com 45 1/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. MFR_CTRL_OPS (D2h) The MFR_CTRL_OPS command sets the switching frequency and light-load operation mode of the MP8796B. Bits Name Access Behavior Default Description [7:3] RESERVED 00000 [2:1] SWITCHING_ FREQUENCY R/W Live 10 00: Set fSW to 400kHz 01: Set fSW to 600kHz 10: Set fSW to 800kHz 11: Set fSW to 1000kHz [0] SKIP_CCM (SYNC) R/W Live 1 0: Pulse-skip mode at light load 1: Forced CCM at light load The default value of D2h is 0x05. MFR_ADDR_PMBUS (D3h) Command MFR_ADDR_PMBUS Format Direct Bit 7 6 5 4 3 2 1 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Function Enable ADDR Default Value 1 0 1 1 0 0 0 0 Bit[7] (enable bit): 1: The address is decided by MFR_ADDR_PMBUS [6:0] 0: The address is decided by the ADDR pin The default value of D3h is 0xB0. MFR_VOUT _OVP_FAULT_LIMIT (D4h) This MFR_VOUT _FAULT_LIMIT command sets the thresholds for UVP and OVP. Bits Name Access Behavior Default Description [7:4] RESERVED 0000 [3:2] OV_EXIT_ TH R/W Live 11 Sets the OVP exit threshold. 00: 10% of VREF 01: 50% of VREF 10: 80% of VREF 11: 102.5% of VREF [1:0] OV_TH R/W Live 10 Sets the OVP entry threshold. 00: 115% of VREF 01: 120% of VREF 10: 125% of VREF 11: 130% of VREF The above thresholds are relative values of the reference voltage. The default value of D4h is 0x0E. |
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