MP8796B datasheet(5/52 Pages) MPS

5 / 52 page

MP8796B – 16V, 30A, SYNCHRONOUS STEP-DOWN CONVERTER WITH PMBUS

MP8796B Rev. 1.0

www.MonolithicPower.com

1/19/2020

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

PIN FUNCTIONS

Pin #

Name

Description

1, 16

Supply voltage. IN supplies power to the internal MOSFET and regulator. Use an input

capacitor to decouple the input rail. Use wide PCB traces and multiple vias to make the

connection.

2, 3

Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to

VIN by the high-side switch during the PWM duty cycle on time. The inductor current drives

SW negative during the off time. Use wide PCB traces to make the connection.

4, 14, 15

PGND

System ground. PGND is the reference ground of the regulated output voltage, and

requires careful consideration during PCB layout. Connect PGND with wide PCB traces.

VDRV

Decoupling input pin for 3.3V driver power supply. Decouple VDRV with a minimum

1µF ceramic capacitor, placed as close to VDRV as possible. X7R or X5R-grade dielectric

ceramic capacitors are recommended. VDRV accepts a 3.3V external bias. If no 3.3V

external bias is provided, connect VDRV to VCC through a 2Ω to 10Ω resistor.

SCL

PMBus clock.

SDA

PMBus data.

ALT#

PMBus alert pin. ALT# is active low. A pull-up resistor connected to 3.3V is required if the

ALT# function is needed.

CTRL

PMBus control pin. CTRL is a digital input pin that turns the regulator on or off with

proper ON_OFF_CONFIG (02h) configuration. Drive CTRL high to turn on the regulator;

drive it low to turn off the regulator. Do not float CTRL.

Power good output. The output of PG is an open-drain signal. PG requires a pull-up

resistor connected to a DC voltage to indicate high if the output voltage is above 90% of

the nominal voltage. There is a PGOOD delay from low to high. PG must be pulled high to

ensure proper operation.

PASS

Passes RUN signals to the next phase.

TAKE

Receives RUN signals from the previous phase. TAKE is used for master detection

during the device’s initial power-up. For the master phase, TAKE must be pulled high

through a resistor. For the slave phase, TAKE is connected to the PASS of the previous

phase.

SET

PWM signal. SET turns the high-side MOSFET on when a RUN signal is present. For

multi-phase operation, tie the SET pins of all phases together.

PS#

Phase shedding. With proper PMBus setting, pull PS# high to enable a slave phase. Pull

it low to disable a slave phase. Connect PS# of the master phase to AGND.

ADDR

PMBus slave address setting pin. Connect a resistor from ADDR to AGND to set the

address of this device.

ISUM

Current-sense output. For single-phase operation, keep ISUM floating. For multi-phase

operation, tie the ISUM pins of all phases together for current sharing.

IREF

Reference current generator amplifier output. Connect a 60.4kΩ or 180kΩ resistor with

1% or greater accuracy to IREF.

VOSNS-

Output voltage sense negative return. VOSNS- is tied directly to the GND sense point

of the load. Connect VOSNS- to AGND if the remote sense is not used.

VOSNS+

Output voltage sense positive return. Connect VOSNS+ to the output voltage sense

positive side to provide feedback voltage to the system. Avoid vias on the VO traces.

AGND

Analog ground. Select AGND as the control-circuit reference point.

MP8796B Datasheet(PDF) 5 Page - Monolithic Power Systems

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