WM8991 datasheet(114/174 Pages) WOLFSON

114 / 174 page

WM8991

Pre-Production

PP, May 2008, Rev 3.1

114

AUDIO INTERFACE OUTPUT AND GPIO TRISTATE

Table 60.

All GPIO[6:1] pins and digital audio interface pins will be tristated by this function, regardless of the

state of other registers which control these pin configurations.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R9 (09h)

AIF_TRIS

Audio Interface and GPIO Tristate

0 = Audio interface and GPIO pins operate normally

1 = Tristate all audio interface and GPIO pins

Table 60 Tri-stating the Audio Interface and GPIO Pins

MASTER MODE BCLK, ADCLRC AND DACLRC ENABLE

The main audio interface pins (BCLK, ADCLRC, ADCDAT, DACLRC and DACDAT) and the

alternative DAC interface pins (BCLK2, DACLRC2, DACDAT2) can be independently programmed to

operate in master mode or slave mode using register bits AIF_MSTR1 and AIF_MSTR2.

When the main audio interface is operating in slave mode, the BCLK, ADCLRC and DACLRC clock

outputs to these pins are by default disabled to allow the digital audio source to drive these pins.

Similarly, when the alternative audio interface is operating in slave mode, the BCLK2 and DACLRC2

clock outputs to these pins are by default disabled.

It is also possible to force the ADCLRC, DACLRC or DACLRC2 to be output using register bits

ADCLRC_DIR and DACLRC_DIR, allowing mixed master and slave modes for the ADCs or the

active DAC audio interface. The active audio interface is selected by register bit AIF_SEL. Enabled

clock outputs on the de-selected audio interface will output logic 0.

When ADCLRC is configured as a GPIO pin (ALRCGPIO1=1), the DACLRC pin is used for the ADCs

and the DACs and will only be disabled in master mode when both ADCs and both DACs are

disabled.

The clock generators for the audio interface are enabled according to the control signals shown in

Figure 78.

Figure 78 Clock Output Control

WM8991 Datasheet(PDF) 114 Page - Wolfson Microelectronics plc