TAS2020 datasheet(18/79 Pages) TI2

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Table 6-9. Noise gate threshold

NG_TH_LVL[2:0]

Configuration

000

-85 dBFs

001

-90 dBFs

010

-95 dBFs

011

-100 dBFs

100 (default)

-105 dBFs

101

-110 dBFs

110

-115 dBFs

111

-120 dBFs

Table 6-10. Noise gate hysteresis timer

NG_HYST_TIMER[1:0]

Configuration

10ms

01 (default)

50ms

100ms

1000ms

6.3.1.4.2 Music Efficiency Mode

When the Music efficiency mode feature is enabled, the device automatically detects low-power signal states

during active playback mode and reduces the overall IQ power consumption to extend the battery life. This

feature is useful for dynamic audio signals with varying signal levels example. Music tracks, voice calls movie

tracks, and so forth.

The device monitors the input audio signal level against the programmed Music efficiency threshold configured

by the MUSIC_EFF_MODE_THR[23:0] register. When the audio signal falls below the threshold, an internal

hysteresis timer is enabled. If the signal level remains below the configured MUSIC_EFF_MODE_THR[23:0] for

the entire duration of the MUSIC_EFF_MODE_TIMER[23:0], the device enters into the Music efficiency mode.

When the device is in Music efficiency mode, the MUSIC_EFF_STATUS bit is set as high and when the device

comes out of music efficiency mode, the status bit is set low.

When the signal level increases above the MUSIC_EFF_MODE_THR[23:0], the device automatically wakes up

the blocks in low IQ mode and continues playing out the audio input signals. The transition from Music efficiency

mode to normal operation occurs with minimal select and pop. While the device is in Music efficiency mode, the

audio channel performance is maintained and does not impact the output signal level or noise.

The MUSIC_EFF_MODE_THR[23:0] and MUSIC_EFF_MODE_TIMER[23:0] registers can be configured using

the PPC3 Software Section 6.4.1.

6.3.2 Faults and Status

During power-up sequencing, the power-on-reset circuit (POR) monitors the VDD and IOVDD pins and holds

device in reset (including all the configuration registers) until the supplies are valid. Any supply voltage dip on

VDD or IOVDD below the UVLO voltage thresholds resets the device immediately along with all the register

configurations.

During operation modes, the device monitors internal device status and fault conditions and can notify the

host of error and status conditions using the IRQZ interrupt pin and internal I2C based interrupt registers. The

interrupt generation in IRQZ pin can be masked by configuring the corresponding Interrupt mask register bit.

Table 6-11 lists the different faults and interrupts that the device monitors and the corresponding configuration

bits to enable/disable the interrupt generation and reading the I2C interrupt status

TAS2020

SLASFD4A – AUGUST 2024 – REVISED JULY 2026

www.ti.com

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