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TAS2020 Datasheet(PDF) 40 Page - Texas Instruments |
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TAS2020 Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 79 page  Table 7-13. TDM_CFG5 Register Field Descriptions (continued) Bit Field Type Reset Description 5 TX_KEEPEN R/W 0h TDM TX SDOUT bus keeper enable. 0h = Disable bus keeper 1h = Enable bus keeper 4 TX_FILL R/W 1h TDM TX SDOUT unused bitfield fill. 0h = Transmit 0 1h = Transmit Hi-Z 3-1 TX_OFFSET[2:0] R/W 1h TDM TX start of frame to time slot 0 offset. 0 TX_EDGE R/W 1h TDM TX launch clock polarity. 0h = Rising edge of SBCLK 1h = Falling edge of SBCLK 7.1.13 TDM_CFG9 Register (Address = 10h) [Reset = 05h] Return to the Summary Table. This register configures device TDM modes. Table 7-14. TDM_CFG9 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h Reserved 6 TEMP_TX R/W 0h TDM TX temp sensor transmit enable. 0h = Disabled 1h = Enabled 5-0 TEMP_SLOT[5:0] R/W 5h TDM TX temp sensor time slot. 7.1.14 TDM_CFG10 Register (Address = 11h) [Reset = 07h] Return to the Summary Table. This register configures device TDM modes Table 7-15. TDM_CFG10 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h Reserved 6 STATUS_TX R/W 0h TDM TX status bits transmit enable. 0h = Disabled 1h = Enabled 5-0 STATUS_SLOT[5:0] R/W 7h TDM TX status bits time slot. 7.1.15 TDM_CFG11 Register (Address = 12h) [Reset = 06h] Return to the Summary Table. This register configures device TDM modes. Table 7-16. TDM_CFG11 Register Field Descriptions Bit Field Type Reset Description 7 PVDD_SLEN R/W 0h TDM TX PVDD time slot length. 0h = Truncate to 8-bits 1h = Left justify to 16-bits 6 PVDD_TX R/W 0h TDM TX PVDD transmit enable. 0h = Disabled 1h = Enabled TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 www.ti.com 40 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: TAS2020 |
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