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TAS2020 Datasheet(PDF) 38 Page - Texas Instruments |
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TAS2020 Datasheet(HTML) 38 Page - Texas Instruments |
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38 / 79 page  7.1.7 DEVICE_CFG_04 Register (Address = 6h) [Reset = 04h] Return to the Summary Table. This register configures various device modes. Table 7-8. DEVICE_CFG_04 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h Reserved 5-4 RESERVED R 0h Reserved 3-2 IRQZ_PIN_CFG[1:0] R/W 1h IRQZ interrupt configuration. IRQZ will assert. 0h = Reserved 1h = on any unmasked latched interrupts 2h = Reserved 3h = for 2-4ms every 4ms on any unmasked latched interrupts 1 RESERVED R 0h Reserved 0 RETRY_WAIT_TIME R/W 0h Retry wait time after device detects error (Valid only for errors with retry options available). 0h = 1.5 sec 1h = 100ms 7.1.8 DEVICE_CFG_05 Register (Address = 7h) [Reset = 00h] Return to the Summary Table. This register configures various device modes. Table 7-9. DEVICE_CFG_05 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h Reserved 6 SAMPLE_RATE_CFG R/W 0h Sampling Rate selection. 0h = Audio data rate is multiple/sub-multiple of 48 Ksps 1h = Audio data rate is multiple/sub-multiple of 44.1 Ksps 5-0 AMP_LVL[5:0] R/W 0h Device Channel Gain setting 17h = 12.471dB 18h = 11.969dB 19h = 11.468dB 20h = 10.966dB 21h = 10.464dB 26h = 1.935dB 27h = 1.434dB 28h = 0.932dB 29h = 0.430dB 2Ah = -0.071dB 7.1.9 TDM_CFG1 Register (Address = 8h) [Reset = 82h] Return to the Summary Table. This register configures device TDM modes. Table 7-10. TDM_CFG1 Register Field Descriptions Bit Field Type Reset Description 7 FRAME_START R/W 1h TDM frame start polarity. 0h = Low to High on FSYNC 1h = High to Low on FSYNC 6 RX_JUSTIFY R/W 0h TDM RX sample justification within the time slot. 0h = Left 1h = Right 5-1 RX_OFFSET[4:0] R/W 1h TDM RX start of frame to time slot 0 offset (SBCLK cycles). TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 www.ti.com 38 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: TAS2020 |
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