TAS2020 datasheet(26/79 Pages) TI2

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Table 6-21. Internal tone clock source selection

(continued)

INTERNAL_TONE_CLK_SEL

Configuration

Tone generator uses internal

oscillator

6.4.3 Digital Audio Serial Interface

The device provides a flexible Audio Serial Interface (ASI) port. The port can be configured to support a variety

of formats including stereo I2S, Left Justified, and TDM. Mono audio playback is available via the SDIN pin. The

SDOUT pin is used to transmit sample streams including PVDD voltage, die temperature, status and audio for

echo reference.

The TDM serial audio port supports up to 16 32-bit time slots at 44.1/48kHz, 8 32-bit time slots at a 88.2/96kHz

sample rate and 4 32-bit time slots at a 176.4/192kHz sample rate. The device supports 2 time slots at 32

bits in width and 4 or 8 time slots at 16, 24 or 32 bits in width. The device automatically detects the number

of time slots and this does not need to be programmed. PCM data sampling rate and SBCLK to FSYNC

ratio detected on the TDM bus is reported back on the read-only register bits FS_RATE_DETECTED[2:0] and

FS_RATIO_DETECTED[3:0] respectively.

Table 6-22. PCM Data Sample Rate Detected

FS_RATE_DETECTED[2:0]

(Read Only)

Setting

000

Reserved

001

14.7kHz / 16kHz

010

22.05kHz / 24kHz

011

29.4kHz / 32kHz

100 (default)

44.1kHz / 48 kHz

101

88.2kHz / 96kHz

110

176.4kHz / 192kHz

111

Error condition

A frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START

RX_EDGE register bit. The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from the

transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified

format and 1 for an I2S format.

The RX_SLEN[1:0] register bits set the length of the RX time slot to 16, 24 or 32 (default) bits. The length of

the audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits. The RX port left

justifies the audio sample within the time slot by default, but this can be changed to right justification via the

RX_JUSTIFY register bit. The device supports mono and stereo down mix playback ([L+R]/2). By default the

device plays-back mono from the time slot equal to the I2C base address offset (set by the AD1 and AD2 pins)

for playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the left time slot,

right time slot or stereo down mix set by the RX_SLOT_R[3:0] and RX_SLOT_L[3:0] register bits.

If time slot selection places reception either partially or fully beyond the frame boundary, the receiver returns a

null sample equivalent to a digitally muted sample.

The TDM port can transmit several sample streams on the SDOUT pin including speaker voltage sense, speaker

current sense, interrupts and status, PVDD voltage and die temperature.

Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin. This can be

configured by setting the TX_EDGE register bit. The TX_OFFSET[2:0] register bits define the number SBCLK

cycles between the start of a frame and the beginning of time slot 0. This is programmed to 0 for Left Justified

TAS2020

SLASFD4A – AUGUST 2024 – REVISED JULY 2026

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