TAS2020 datasheet(31/79 Pages) TI2

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addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit.

Each transfer operation begins with the controller device driving a start condition on the bus and ends with the

controller device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the

clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and

a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock

period.

The controller device drives a start condition followed by the 7-bit target address and the read/write (R/W)

bit to open communication with another device and then waits for an acknowledgment condition. The target

device holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the

controller device transmits the next byte of the sequence. Each target device is addressed by a unique 7-bit

target address plus the R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus

using a wired-AND connection.

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TAS2020

SLASFD4A – AUGUST 2024 – REVISED JULY 2026

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TAS2020 Datasheet(PDF) 31 Page - Texas Instruments