TAS2020 datasheet(72/79 Pages) TI2

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8.3 What to Do and What Not to Do

• Additional 2mA to 3mA leakage current from VDD supply is expected when IRQZ pin is pulled high.

• IRQZ pin should be left floating or grounded on the board instead of connecting pull-up resistor to avoid

leakage current issue.

• I2C polling based interrupt mechanism can be implemented in host instead of HW pin based interrupt from

device.

• For HW pin based interrupt, recommend to change IRQZ polarity to active high instead of the default active

low state. This can be done by writing ‘1’ to IRQZ_POL register in IO_CFG_02 register in Page0 (Section

7.1).

8.4 Power Supply Recommendations

TAS2020 power up sequence of supply rails and ASI clocks can be applied in any order as long as SDZ pin is

held low. Once all supplies and ASI clocks are stable the SDZ pin can be pulled high to initialize the device.

For power down sequence recommedation is to mute the device first. Following that SDZ pin must be pulled low

before supply rails are ramped down in any order.

Once all the supplies are valid and SDZ pin is released to high, the digital core voltage regulator powers up,

and starts the internal initialization sequence. After a hardware or software reset, additional I2C commands to the

device should be delayed by at-least 300us to allow the device internal blocks to be initialized.

Supply voltage needs to be 2.2V or higher at all times including ripple conditions to avoid device UVLO.

8.5 Layout

8.5.1 Layout Guidelines

• Use wide traces for signals that carry high current and avoid VIAs wherever possible. If VIAs can't be

avoided, multiple VIAs should be added to enable low parasitic inductance and high current capability. These

include traces for PVDD, VDD, PGND, GND, OUT_P and OUT_N.

• PGND signal should be directly connected and shorted to the ground plane of board to minimize parasitic

inductance. Common inductance between ground pins (eg GND and PGND common routing) before

connecting to ground plane should be avoided.

• The coupling between high switching signal traces like OUT_P, OUT_N, SW, should be avoided from

sensitive low voltage signals.

• Minimize capacitance between high switching lines like OUT_P, OUT_N, SW, to ground/static nodes. Larger

capacitance will result in efficiency drop. Coupling between OUT_P and OUT_N will also cause degraded

efficiency.

• Decoupling capacitors should be placed close to the device. Smallest possible package size is recommended

for the decaps to achieve best performance from device. DREG, VDD, IOVDD, PVDD low ESL (C4 Cap, C6

cap) are recommended to be 0201 case size or lower. VIAs between decapacitors and device pins should be

avoided, or multiple VIAs added to minimize parasitic inductances.

• All decoupling capacitor's ground terminal should be strongly connected to the ground plane with multiple

ground VIAs. The ground routing loop between the cap ground and the device ground pins should be

minimized.

• For VDD Y-bridge functionality, the routing from the host PMIC to the device VDD should be wide supply

plane trace with minimal routing parasitic inductance.

• For the capacitor between GREG-PVDD (C9 cap), PVDD side of capacitor should not be connected directly

to the PVDD decoupling capacitors (C6, C7 and C8), and should be connected as close as possible to the

device PVDD pin.

TAS2020

SLASFD4A – AUGUST 2024 – REVISED JULY 2026

www.ti.com

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