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TAS2020 Datasheet(PDF) 19 Page - Texas Instruments |
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TAS2020 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 79 page  Table 6-11. Faults and Interrupts Category Interrupt Interrupt Mask register bit Default Mask status Interrupt Latched status bit Limiter & Brown out protection Section 6.4.2.4 Brownout detected INT_MASK0[3] Not Masked INT_LTCH0[3] BOP Active INT_MASK0[2] Not Masked INT_LTCH0[2] BOP infinite hold INT_MASK0[7] Not Masked INT_LTCH0[7] Limiter Active INT_MASK0[4] Not Masked INT_LTCH0[4] Limiter attenuation INT_MASK0[6] Not Masked INT_LTCH0[6] Supply below inflection point INT_MASK0[5] Not Masked INT_LTCH0[5] Supply Voltage Monitors PVDD Over voltage INT_MASK3[2] Not Masked INT_LTCH3[2] PVDD Under voltage INT_MASK1[7] Not Masked INT_LTCH1[7] Thermal protection Section 6.4.4 Thermal warning at 135C INT_MASK1[4] Masked INT_LTCH1[4] Thermal warning at 125C INT_MASK1[3] Masked INT_LTCH1[3] Thermal warning at 115C INT_MASK1[2] Masked INT_LTCH1[2] Thermal warning at 105C INT_MASK1[1] Masked INT_LTCH1[1] Over temperature error INT_MASK3[7] Not Masked INT_LTCH3[7] Clock protection Watchdog expiry INT_MASK2[7] Not Masked INT_LTCH2[7] Frame out of sync INT_MASK2[5] Masked INT_LTCH2[5] PLL clock error INT_MASK2[4] Not Masked INT_LTCH2[4] TDM clock error INT_MASK2[3] Masked INT_LTCH2[3] Pre-Power-up Clock error INT_MASK4[2] Not Masked INT_LTCH4[2] Clock ratio change error INT_MASK2[2] Masked INT_LTCH2[2] Fs change error INT_MASK2[1] Masked INT_LTCH2[1] Fs invalid error INT_MASK2[0] Masked INT_LTCH2[0] Frame out of sync INT_MASK2[5] Masked INT_LTCH2[5] Internal PLL Clock error INT_MASK2[4] Not Masked INT_LTCH2[4] Digital watchdog INT_MASK2[7] Not Masked INT_LTCH2[7] Other Protections & Status Class-D Over current error INT_MASK3[3] Not Masked INT_LTCH3[3] Device Active INT_MASK0[1] Masked INT_LTCH0[1] 6.3.2.1 Interrupt generation and clearing The IRQZ is an open drain output that asserts low during unmasked fault conditions and therefore must be pulled up with a resistor to IOVDD. An internal pull up resistor (18kΩ) is provided in the device and can be assessed by setting the IRQZ_PU register bit. The interrupt generation on IRQZ pin can be configured using IRQZ_PIN_CFG[1:0] register. For the interrupts that have auto retry feature, the retry timer can be configured using RETRY_WAIT_TIME register. The interrupt pin polarity can be changed from the default case of Active Low to Active high by setting the IRQZ_POL register bit high. Any latched interrupt can be cleared by setting INT_CLR_LTCH bit high. This is self clearing bit and automatically gets updated to low once the interrupt is cleared. Interrupts can also be cleared by hardware shutdown by pulling the SDZ pin low, or by software reset using SW_RESET bit. Table 6-12. IRQZ pin configuration IRQZ_PIN_CFG[1:0] Configuration 00 Reserved 01(default) Interrupt generated on any unmasked latched interrupt 10 Reserved www.ti.com TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TAS2020 |
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