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TAS2020 Datasheet(PDF) 51 Page - Texas Instruments |
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TAS2020 Datasheet(HTML) 51 Page - Texas Instruments |
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51 / 79 page  7.2 PAGE 1 Registers Table 7-42 lists the memory-mapped registers for the PAGE 1 registers. All register offset addresses not listed in Table 7-42 should be considered as reserved locations and the register contents should not be modified. Table 7-42. PAGE 1 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.2.1 Eh DEV_PERF_TUNING_07 Device performance tuning register Section 7.2.2 2Bh DEV_PERF_TUNING_04 Device performance Tuning register Section 7.2.3 64h I2C_CKSUM I2C Checksum Section 7.2.4 7.2.1 PAGE Register (Address = 0h) [Reset = 00h] Return to the Summary Table. The device's memory map is divided into pages and books. This register sets the page. Table 7-43. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255 7.2.2 DEV_PERF_TUNING_07 Register (Address = Eh) [Reset = 0Bh] Return to the Summary Table. Device performance tuning register Table 7-44. DEV_PERF_TUNING_07 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h Reserved 5-4 RESERVED R 0h Reserved 3-0 DEV_PERF_TUNING_07[ 3:0] R/W Bh Device performance tuning register 0h = External PVDD mode tuning Bh = Reserved 7.2.3 DEV_PERF_TUNING_04 Register (Address = 2Bh) [Reset = 80h] Return to the Summary Table. Device performance Tuning register Table 7-45. DEV_PERF_TUNING_04 Register Field Descriptions Bit Field Type Reset Description 7-0 DEV_PERF_TUNING_04[ 7:0] R/W 80h Device performance tuning. PPC3 software generates the correct configuration required 7.2.4 I2C_CKSUM Register (Address = 64h) [Reset = 00h] Return to the Summary Table. Returns I2C checksum. www.ti.com TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: TAS2020 |
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