LAN9313 datasheet(137/398 Pages) SMSC

137 / 398 page

Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

137

Revision 1.2 (04-08-08)

DATASHEET

Clock synchronization and hardware processing between the network data and the time stamp capture

hardware causes the time stamp point to be slightly delayed. The host software can account for this

delay, as it is fairly deterministic. Table 10.2 details the time stamp capture delay as a function of the

mode of operation. Refer to Chapter 7, "Ethernet PHYs," on page 84 for details on these modes.

Once the packet type is matched, according to Table 10.1, and the Frame Check Sequence (FCS) is

verified, the following occurs:

The time stamp is loaded into the corresponding ports’ capture registers:

–On Reception: Port x 1588 Clock High-DWORD Receive Capture Register

(1588_CLOCK_HI_RX_CAPTURE_x) and Port x 1588 Clock Low-DWORD Receive Capture

–On Transmission: Port x 1588 Clock High-DWORD Transmit Capture Register

(1588_CLOCK_HI_TX_CAPTURE_x) and Port x 1588 Clock Low-DWORD Transmit Capture

The Sequence ID and Source UUID are loaded into the corresponding ports’ registers:

–On Reception: Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register

(1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x) and Port x 1588 Source UUID Low-

DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x)

–On Transmission: Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture

Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x)

The corresponding maskable interrupt flag is set in the 1588 Interrupt Status and Enable Register

(1588_INT_STS_EN). (Refer to Section 10.6, "IEEE 1588 Interrupts," on page 140 for information

on IEEE 1588 interrupts.)

Note:

Packets that do not contain an integral number of octets are not considered valid and do not

cause a capture.

10.2.1

Capture Locking

The corresponding ports’ clock capture, sequence ID, and source UUID registers can be optionally

locked when a capture event occurs, preventing them from being overwritten until the host clears the

corresponding interrupt flag in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN).

This is accomplished by setting the corresponding lock enable bit(s) in the 1588 Configuration Register

(1588_CONFIG). Each port has two lock enable control bits within this register, which allow the receive

and transmit portions of each port to be locked independently. In addition, a lock enable bit is provided

for each time stamp enabled GPIO (LOCK_ENABLE_GPIO_8 and LOCK_ENABLE_GPIO_9) which

prevents the corresponding GPIO clock capture registers from being overwritten when the GPIO

interrupt in 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) is set. Refer to Section

13.1.4.22, "1588 Configuration Register (1588_CONFIG)," on page 185 for additional information on

the capture locking related bits.

Table 10.2 Time Stamp Capture Delay

MODE OF OPERATION

DELAY (+/- 10 nS)

100 Mbps

30 nS

10 Mbps

120 nS

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