LAN9313 datasheet(141/398 Pages) SMSC

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Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

141

Revision 1.2 (04-08-08)

DATASHEET

Chapter 11 General Purpose Timer & Free-Running Clock

This chapter details the LAN9313/LAN9313i General Purpose Timer (GPT) and the Free-Running

Clock.

11.1

General Purpose Timer

The LAN9313/LAN9313i provides a 16-bit programmable General Purpose Timer that can be used to

generate periodic system interrupts. The resolution of this timer is 100uS.

The GPT loads the General Purpose Timer Count Register (GPT_CNT) with the value in the

GPT_LOAD field of the General Purpose Timer Configuration Register (GPT_CFG) when the

TIMER_EN bit of the General Purpose Timer Configuration Register (GPT_CFG) is asserted (1). On

a chip-level reset, or when the TIMER_EN bit changes from asserted (1) to de-asserted (0), the

GPT_LOAD field is initialized to FFFFh. The General Purpose Timer Count Register (GPT_CNT) is

also initialized to FFFFh on reset. Software can write a pre-load value into the GPT_LOAD field at any

time (e.g. before or after the TIMER_EN bit is asserted).

Once enabled, the GPT counts down until it reaches 0000h, or until a new pre-load value is written to

the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT interrupt status

bit (GPT_INT) in the Interrupt Status Register (INT_STS), asserts the IRQ interrupt (if GPT_INT_EN is

set in the Interrupt Status Register (INT_STS)), and continues counting. GPT_INT is a sticky bit. Once

this bit is asserted, it can only be cleared by writing a 1 to the bit. Refer to Section 5.2.5, "General

Purpose Timer Interrupt," on page 55 for additional information on the GPT interrupt.

11.2

Free-Running Clock

The Free-Running Clock (FRC) is a simple 32-bit up-counter that operates from a fixed 25MHz clock.

The current FRC value can be read via the Free Running 25MHz Counter Register (FREE_RUN). On

assertion of a chip-level reset, this counter is cleared to zero. On de-assertion of a reset, the counter

is incremented once for every 25MHz clock cycle. When the maximum count has been reached, the

counter rolls over to zeros. The FRC does not generate interrupts.

Note:

The free running counter can take up to 160nS to clear after a reset event.

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