C167CS datasheet(309/517 Pages) INFINEON

309 / 517 page

C167CS

Derivatives

The Real Time Clock

User’s Manual

14-3

V2.0, 2000-07

RTC Register Access

The actual value of the RTC is represented by the 3 registers T14, RTCL and RTCH. As

these registers are concatenated to build the RTC counter chain, internal overflows

occur while the RTC is running. When reading or writing the RTC value make sure to

account for such internal overflows in order to avoid reading/writing corrupted values.

When reading/writing e.g. 0000H to RTCH and then accessing RTCL will produce a

corrupted value as RTCL may overflow before it can be accessed. In this case, however,

RTCH would be 0001H. The same precautions must be taken for T14 and T14REL.

RTC Interrupt Generation

The RTC interrupt shares the XPER3 interrupt node with the PLL/OWD interrupt. This is

controlled by the interrupt subnode control register ISNC. The interrupt handler can

determine the source of an interrupt request via the separate interrupt request and

enable flags (see Figure 14-3) provided in register ISNC.

Note: If only one source is enabled no additional software check is required, of course.

Figure 14-3

RTC Interrupt Logic

If T14 interrupts are to be used both stages, the interrupt node (XP3IE = ‘1’) and the RTC

subnode (RTCIE = ‘1’) must be enabled.

Please note that the node request bit XP3IR is automatically cleared when the interrupt

handler is vectored to, while the subnode request bit RTCIR must be cleared by software.

MCA04464

RTCIE

Intr. Enable

PLLIR

RTCIR

PLL/OWD

Interrupt

T14

Interrupt

XPER3

Interrupt

Node

PLLIE

Intr. Request

Interrupt

Controller

C167CS Datasheet(PDF) 309 Page - Infineon Technologies AG

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