SH7021 datasheet(119/509 Pages) RENESAS

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RENESAS 101

8.2.3

Wait State Control Register 2 (WCR2)

Wait state control register 2 is a 16-bit read/write register that controls the number of states for

accessing each area with a DMA single address mode transfer and whether wait states are used.

WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or by the

standby mode.

Bit:

Bit name:

DRW7

DRW6

DRW5

DRW4

DRW3

DRW2

DRW1

DRW0

Initial value:

R/W:

R/W

Bit:

Bit name:

DWW7

DWW6

DWW5

DWW4

DWW3

DWW2

DWW1

DWW0

Initial value:

R/W:

R/W

•

Bits 15–8 (wait state control during single-mode DMA transfer (DRW7–DRW0)): DRW7–

DRW0 determine the number of states in single-mode DMA memory read cycles for each area

and whether or not to sample the

WAIT signal. Bits DRW7–DRW0 correspond to areas 7–0,

respectively. If a bit is cleared to 0, the

WAIT signal is not sampled during the single-mode

DMA memory read cycle for the corresponding area. If it is set to 1, sampling takes place.

For the external memory spaces of areas 1, 3–5, and 7, single-mode DMA memory read cycles

are completed in one state when the corresponding bits are cleared to 0. When they are set to 1,

the number of wait states is 2 plus the wait states from the

WAIT signal. For the external

memory space of areas 0, 2, and 6, single-mode DMA memory read cycles are completed in

one state plus the long wait state number (set in wait state controller 3 (WCR3)) when the

corresponding bits are cleared to 0. When they are set to 1, the number of wait states is 1 plus

the long wait state; when the

WAIT signal is at low level as well, a wait state is inserted.

The DRAM space (area 1) finishes the column address output cycle in one state (short pitch)

when the DRW1 bit is 0, and in 2 states plus the wait states from the

WAIT signal (long pitch)

when DRW1 is 1. The single-mode DMA memory read cycle of the address/data multiplexed

I/O space (area 6) is 4 states plus the wait states from the

WAIT signal, regardless of the

setting of the DRW6 bit.

Table 8.4 summarizes single-mode DMA memory read cycle state information.

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