SH7021 datasheet(123/509 Pages) RENESAS

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RENESAS 105

Bit:

Bit name:

CW2

RASD

TPC

CDTY

MXE

MXC1

MXC0

Initial value:

R/W:

R/W

Bit:

Bit name:

—

Initial value:

R/W:

—

•

Bit 15 (dual-CAS or dual-WE select bit (CW2)): When accessing a 16-bit bus width space,

CW2 selects the dual-CAS or the dual-WE method. When cleared to 0, the

CASH, CASL, and

WRL signals are valid ; when set to 1, the CASL, WRH, and WRL signals are valid. When

accessing an 8-bit space, only

CASL and WRL signals are valid, regardless of CW2 settings.

Bit 15L: CW2

Description

Dual-CAS: CASH, CASL, and WRL signals are valid (initial value)

Dual-WE: CASL, WRH, and WRL signals are valid

•

Bit 14 (RAS down (RASD)): When DRAM access pauses, RASD determines whether to keep

RAS low while waiting for the next DRAM access (RAS down mode) or return it to high

(RAS up mode). When cleared to 0, the

RAS signal returns to high; when set to 1, it stays at

low.

Bit 14: RASD

Description

RAS up mode: Return RAS signal to high and wait for the next DRAM

access (initial value)

RAS down mode: Keep RAS signal low and wait for the next DRAM

access

•

Bit 13 (RAS precharge cycle count (TPC)): TPC selects whether the

RAS signal precharge

cycle (TP) will be 1 state or 2. When TPC is cleared to 0, a 1-state precharge cycle is inserted;

when 1 is set, a 2-state precharge cycle is inserted.

Bit 13: TPC

Description

Inserts 1-state precharge cycle (initial value)

Inserts 2-state precharge cycle

SH7021 Datasheet(PDF) 123 Page - Renesas Technology Corp

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