SH7021 datasheet(120/509 Pages) RENESAS

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Table 8.4

Single-Mode DMA Memory Read Cycle States (External Memory Space)

Description

Single-Mode DMA Memory Read Cycle States

(External Memory Space)

Bits 15–8:

DRW7–DRW0

WAIT Pin Input

Signal

External Memory

Space

DRAM Space

Multiplexed

I/O

Not sampled during

single-mode DMA

memory read cycle*

Areas 1, 3–5,7: 1 state,

fixed

Areas 0, 2, 6: 1 state +

long wait state

Column address

cycle: 1 state,

fixed (short

pitch)

4 states +

wait states

from WAIT

Sampled during

single-mode DMA

memory read cycle

(initial value)

Areas 1, 3–5, 7: 2 states

+ wait states from WAIT

Areas 0, 2, 6: 1 state +

long wait state + Wait

state from WAIT

Column address

cycle: 2 states +

wait state from

WAIT (long

pitch)

Note:

Sampled in the address/data multiplexed I/O space.

•

Bits 7–0 (single-mode DMA memory write wait state control (DWW7–DWW0)): DWW7–

DWW0 determine the number of states in single-mode DMA memory write cycles for each

area and whether or not to sample the

WAIT signal. Bits DWW7–DWW0 correspond to areas

7–0, respectively. If a bit is cleared to 0, the

WAIT signal is not sampled during the single-

mode DMA memory write cycle for the corresponding area. If it is set to 1, sampling takes

place.

The number of states for areas accesses based on bit settings are the same as indicated for

single-mode DMA memory read cycles. See bits 15–8, wait state control during single-mode

DMA memory transfer (DRW7–DRW0), for details.

Table 8.5 summarizes single-mode DMA memory write cycle state information.

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