SH7021 datasheet(243/509 Pages) RENESAS

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Bit 1 (timer synchro 1 (SYNC1)): SYNC1 selects the synchronizing mode for channel 1.

Bit 1: SYNC1

Description

The timer counter for channel 1 (TCNT1) operates independently

(Preset/clear of TCNT1 is independent of other channels) (initial value)

Channel 1 operates synchronously. Synchronized preset/clear of

TNCT1 enabled.

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Bit 0 (timer synchro 0 (SYNC0)): SYNC0 selects the synchronizing mode for channel 0.

Bit 0: SYNC0

Description

The timer counter for channel 0 (TCNT0) operates independently

(Preset/clear of TCNT0 is independent of other channels) (initial value)

Channel 0 operates synchronously. Synchronized preset/clear of

TNCT0 enabled.

10.2.3

Timer Mode Register (TMDR)

The timer mode register (TMDR) is an eight-bit read/write register that selects the PWM mode for

channels 0–4, sets the phase counting mode for channel 2, and sets the conditions for the overflow

flag (OVF). TMDR is initialized to H'80 or H'00 by a reset or the standby mode.

Bit:

Bit name:

—

MDF

FDIR

PWM4

PWM3

PWM2

PWM1

PWM0

Initial value:

R/W:

—

R/W

Note:

Undefined

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Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1.

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Bit 6 (phase counting mode (MDF)): MDF selects the phase counting mode for channel 2.

Bit 6: MDF

Description

Channel 2 operates normally (initial value)

Channel 2 operates in phase counting mode

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