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SH7021 Datasheet(PDF) 244 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 244 Page - Renesas Technology Corp |
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244 / 509 page  228 RENESAS When the MDF is set to 1 to select the phase counting mode, the timer counter (TCNT2) becomes an up/down counter and the TCLKA and TCLKB pins become count clock input pins. TCNT2 counts on both the rising and falling edges of TCLKA and TCLKB, with the increment/decrement chosen as follows: Count Direction Decrement Increment TCLKA pin Rising High Falling Low Rising High Falling Low TCLKB pin L Rising High Falling High Falling Low Rising In the phase counting mode, selections for external clock edge made in the CKEG1 and CKEG0 bits of the timer control register 2 (TCR2) and the selection for counter clock made in the TPSC2 –TPSC0 bits are ignored. The phase counting mode described above takes priority. Settings for counter clear conditions in the CCLR1 and CCLR0 bits of TCR2 and settings for timer I/O control register 2 (TIOR2), timer interrupt enable register (TIER2) and timer status register 2 (TSR2) compare match/input capture functions and interrupts, however, are valid even in the phase counting mode. • Bit 5 (flag direction (FDIR)): FDIR selects the setting condition for the overflow flag (OVF) in timer status register 2 (TSR2). This bit is valid no matter which mode channel 2 is operating in. Bit 5: FDIR Description 0 OVF of TSR2 is set to 1 when TCNT2 overflows or underflows (initial value) 1 OVF of TSR2 is set to 1 when TCNT2 overflows • Bit 4 (PWM Mode 4 (PWM4)): PWM4 selects the PWM mode for channel 4. When the PWM4 bit is set to 1 and the PWM mode entered, the TIOCA4 pin becomes a PWM output pin. 1 is output on a compare match of general register A4 (GRA4); 0 is output on a compare match of general register B4 (GRB4). When the complementary PWM mode or reset- synchronized PWM mode are set by the CMD1 and CMD0 bits of the timer function control register (TFCR), the setting of this bit is ignored in favor of the settings of CMD1 and CMD0. Bit 4: PWM4 Description 0 Channel 4 operates normally (initial value) 1 Channel 4 operates in PWM mode |
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