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Bit:

Bit name:

PB7DR

PB6DR

PB5DR

PB4DR

PB3DR

PB2DR

PB1DR

PB0DR

Initial value:

R/W:

R/(W)*

Note:

Bits set to TPC output by NDERA or NDERB are read-only.

11.2.3

Next Data Register A (NDRA)

NDRA is an eight-bit read/write register that stores the next output data for TPC output groups 1

and 0 (TP7–TP0). When used for TPC output, the contents of the NDRA are transferred to the

corresponding PBDR bits when the ITU compare match specified in the TPC output control

The address of the NDRA differs depending on whether TPCR settings select the same trigger or

different triggers for TPC output groups 1 and 0. When reset, NDRA is initialized to H'00. It is not

initialized by standby mode.

Same Trigger for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered by

the same compare match, the address of the NDRA is H'FFFFF5. The 4 upper bits becomes group

1 and the 4 lower bits become group 0. Address H'5FFFFF7 in such cases consists entirely of

reserved bits. These bits cannot be modified and always read as 1.

Address H'5FFFFF5:

•

Bits 7–4 (next data 7–4 (NDR7–NDR4)): NDR7-NDR4 store the next output data for TPC

output group 1.

•

Bits 3–0 (next data 3–0 (NDR3–NDR0)): NDR3-NDR0 store the next output data for TPC

output group 0.

Bit:

Bit name:

NDR7

NDR6

NDR5

NDR4

NDR3

NDR2

NDR1

NDR0

Initial value:

R/W:

R/W

SH7021 Datasheet(PDF) 324 Page - Renesas Technology Corp

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