SH7021 datasheet(327/509 Pages) RENESAS

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RENESAS 311

Different Triggers for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered

by different compare matches, the address of the upper 4 bits of NDRB (group 3) is H'5FFFFF4

and the address of the lower 4 bits of NDRB (group 2) is H'5FFFFF6. Bits 3-0 of address

H'5FFFFF4 and bits 7–4 of address H'5FFFFF6 are reserved bits. These bits always read as 1. The

write value should always be 1.

Address H'5FFFFF4:

•

Bits 7–4 (next data 15–12 (NDR15–NDR12)): NDR15–NDR12 store next output data for TPC

output group 3.

•

Bits 3–0 (reserved): These bits always read as 1. The write value should always be 1.

Bit:

Bit name:

NDR15

NDR14

NDR13

NDR12

—

Initial value:

R/W:

R/W

—

Address H'5FFFFF6:

•

Bits 7–4 (reserved): These bits always read as 1. The write value should always be 1.

•

Bits 3–0 (next data 11–8 (NDR11–NDR8)): NDR11–NDR8 store next output data for TPC

output group 2.

Bit:

Bit name:

—

NDR11

NDR10

NDR9

NDR8

Initial value:

R/W:

—

R/W

11.2.5

Next Data Enable Register A (NDERA)

NDERA is an eight-bit read/write register that enables TPC output groups 1 and 0 (TP7–TP0) on a

bit-by-bit basis.

When the bits enabled for TPC output by NDERA generate the ITU compare match selected in the

TPC output control register, the value of the next data register A (NDRA) is automatically

transferred to the corresponding PBDR bits and the output value is updated. For disabled bits,

there is no transfer and the output value does not change. When reset, NDERA is initialized to

H'00. It is not initialized by standby mode.

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