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SH7021 Datasheet(PDF) 330 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 330 Page - Renesas Technology Corp |
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330 / 509 page ![]() 314 RENESAS Bits 3 and 2 (group 1 compare-match select 1 and 0 (G1CMS1 and G1CMS0)): G1CMS1 and G1CMS0 select the ITU channel that triggers TPC output group 1 (TP7–TP4). Bit 3: G1CMS1 Bit 2: G1CMS0 Description 0 0 TPC output group 1 (TP7–TP4) output is triggered by compare-match in ITU channel 0 1 TPC output group 1 (TP7–TP4) output is triggered by compare-match in ITU channel 1 1 0 TPC output group 1 (TP7–TP4) output is triggered by compare-match in ITU channel 2 1 TPC output group 1 (TP7–TP4) output is triggered by compare-match in ITU channel 3 (initial value) • Bits 1 and 0 (group 0 compare-match select 1 and 0 (G0CMS1 and G0CMS0)): G0CMS1 and G0CMS0 select the ITU channel that triggers TPC output group 0 (TP3–TP0). Bit 1: G0CMS1 Bit 0: G0CMS0 Description 0 0 TPC output group 0 (TP3–TP0) output is triggered by compare-match in ITU channel 0 1 TPC output group 0 (TP3–TP0) output is triggered by compare-match in ITU channel 1 1 0 TPC output group 0 (TP3–TP0) output is triggered by compare-match in ITU channel 2 1 TPC output group 0 (TP3–TP0) output is triggered by compare-match in ITU channel 3 (initial value) 11.2.8 TPC Output Mode Register (TPMR) TPMR is an eight-bit read/write register that selects between the TPC's ordinary output and non- overlap output modes in group units. During non-overlap operation, the output waveform cycle is set in ITU general register B (GRB) for use as the output trigger and a non-overlap period is set in general register A (GRA). The output value then changes on compare matches A and B. For details, see section 11.3.4, TPC Output Non-Overlap Operation. TPMR is initialized to H'F0 on a reset. It is not initialized in standby mode. Bit: 7 6 5 4 3 2 1 0 Bit name: — — — — G3NOV G2NOV G1NOV G0NOV Initial value: 1 1 1 1 0 0 0 0 R/W: — — — — R/W R/W R/W R/W |
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