SH7021 datasheet(326/509 Pages) RENESAS

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11.2.4

Next Data Register B (NDRB)

NDRB is an eight-bit read/write register that stores the next output data for TPC output groups 3

and 2 (TP15–TP8). When used for TPC output, the contents of the NDRB are transferred to the

corresponding PBDR bits when the ITU compare match specified in the TPC output control

The address of the NDRB differs depending on whether TPCR settings select the same trigger or

different triggers for TPC output groups 3 and 2. When reset, NDRB is initialized to H'00. It is not

initialized by standby mode.

Same Trigger for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by the

same compare match, the address of the NDRB is H'FFFFF4. The 4 upper bits becomes group 3

and the 4 lower bits become group 2. Address H'5FFFFF6 becomes completely reserved bits.

These bits always read as 1, and the write value should always be 1.

Address H'5FFFFF4:

•

Bits 7–4 (next data 15–12 (NDR15–NDR12)): NDR15–NDR12 store next output data for TPC

output group 3.

•

Bits 3–0 (next data 11–8 (NDR11–NDR8)): NDR11–NDR8 store next output data for TPC

output group 2.

Bit:

Bit name:

NDR15

NDR14

NDR13

NDR12

NDR11

NDR10

NDR9

NDR8

Initial value:

R/W:

R/W

Address H'5FFFFF6:

•

Bits 7–0 (reserved): These bits always read as 1. The write value should always be 1.

Bit:

Bit name:

—

Initial value:

R/W:

—

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