7477 datasheet(234/361 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

2-8

APPLICATION

2.2 Interrupts

7470

7471

7477

7478

2.2.2. Processor status register (PS)

The Processor status register consists of 8 bits.

Figure 2.2.2 shows the structure of the Processor status register. Bit 2 related to interrupts is described

below.

2 Interrupt disable flag: b2

The interrupt disable flag controls the acceptance of interrupt requests other than the BRK instruction.

When this flag is “1,” the acceptance of interrupt requests is disabled. When the flag is “0,” the

acceptance of interrupt requests is enabled. The instruction to set this flag to “1” is the SEI instruction

and the instruction to set this flag to “0” is the CLI instruction.

At a branch to an interrupt processing routine, this flag is automatically set to “1,” thereby multiple

interrupts are disabled. To use multiple interrupt, set this flag to “0” by using the CLI instruction in

the interrupt processing routine.

Fig. 2.2.2 Structure of Processor status register

Processor status register

Undefined

Processor status register (PS)

Unde-

fined

Flag name

: Carry flag

: Zero flag

: Interrupt disable flag

: Decimal mode flag

: Break flag

: Index X mode flag

: Overflow flag

: Negative flag

The value in

denotes the initial value immediately after reset release.

7477 Datasheet(PDF) 234 Page - Renesas Technology Corp