7480 datasheet(65/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

1-48

HARDWARE

1.11 Interrupts

(3) CNTR0 and CNTR1 Interrupts

When a rising edge or a falling edge of the input signal to the CNTR0 or the CNTR1 pin is detected,

an interrupt request is generated. The edge polarity to be detected can be selected by the CNTR0

edge selection bit or the CNTR1 edge selection bit of the edge polarity selection register.

• State after system is released from reset

After system is released from reset, the port pins with the alternative functions of CNTR pins are

placed in the input mode, and their edge selection bits are held all ‘0’ also. In such conditions,

though an interrupt request is generated by detecting a falling edge of the CNTR0 or CNTR1 pin,

the interrupt request cannot be accepted because the corresponding interrupt enable bit is ‘0’ and

the interrupt disable flag is ‘1’.

Note: The CNTR0 and CNTR1 pins have the alternative functions of I/O port pins P40 and P41,

respectively. When these pins are used as input port pins, valid edges can still be detected

because the 7480 Group and 7481 Group does not have the function to switch the CNTR pins

to input port pins. Therefore, when these pins are used as input port pins, clear all the

corresponding interrupt enable bits to ‘0’ (disabled).

(4) Timer X, Timer Y, Timer 1, and Timer 2 Interrupts

At an underflow in each timer, the corresponding interrupt request is generated.

For timer X and timer Y, refer to Section 1.12 Timer X and Timer Y, and for timer 1 and timer 2,

refer to Section 1.13 Timer 1 and Timer 2.

(5) Serial I/O Receive Interrupt, Serial I/O Transmit Interrupt, and Bus Arbitration Interrupt

• Serial I/O receive interrupt

During serial I/O reception, a serial I/O receive interrupt request is generated when the received

data stored completely in the receive shift register is transferred to the receive buffer register.

• Serial I/O transmit interrupt

During serial I/O transmission, a serial I/O transmit interrupt request is generated when the transmit

buffer register is emptied or the transmit shift operation is complete.

• Bus arbitration interrupt

In the bus collision detection enable state during the serial I/O communication, the mismatch of

levels between transmitter pin TxD and receiver pin RxD generates a bus arbitration interrupt

request.

The bus collision detection can be enabled by setting the bus collision detection enable bit of the

bus collision detection control register.

For serial I/O, refer to Section 1.14 Serial I/O.

(6)

A-D Conversion Complete Interrupt

When A-D conversion is completed, an A-D conversion complete interrupt request is generated.

For A-D conversion, refer to Section 1.15 A-D Converter.

(7)

BRK Instruction Interrupt

The BRK instruction interrupt is a non-maskable software interrupt. Program branches to the jump

address stored in the vector address when the BRK instruction is executed.

For the BRK instruction, refer to the section of the BRK instruction in SERIES 740 <SOFTWARE>

USER’S MANUAL.

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