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7480 Datasheet(PDF) 16 Page - Renesas Technology Corp |
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7480 Datasheet(HTML) 16 Page - Renesas Technology Corp |
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16 / 337 page ![]() List of Figures vi 7480 Group and 7481 Group User’s Manual CHAPTER 3 APPENDICES Figure 3.1.1 Port Pi Registers (i = 0 to 5) ................................................................................ 3-2 Figure 3.1.2 Port Pi Direction Registers (i = 0, 1, 4, 5) .......................................................... 3-2 Figure 3.1.3 Port P0 Pull-up Control Register ........................................................................... 3-3 Figure 3.1.4 Port P1 Pull-up Control Register ........................................................................... 3-3 Figure 3.1.5 Port P4P5 Input Control Register ......................................................................... 3-4 Figure 3.1.6 Edge Polarity Selection Register ........................................................................... 3-5 Figure 3.1.7 A-D Control Register ............................................................................................... 3-6 Figure 3.1.8 A-D Conversion Register ........................................................................................ 3-6 Figure 3.1.9 STP Instruction Operation Control Register ......................................................... 3-7 Figure 3.1.10 Transmit/Receive Buffer Register ........................................................................ 3-8 Figure 3.1.11 Serial I/O Status Register .................................................................................... 3-8 Figure 3.1.12 Serial I/O Control Register ................................................................................... 3-9 Figure 3.1.13 UART Control Register ......................................................................................... 3-9 Figure 3.1.14 Baud Rate Generator .......................................................................................... 3-10 Figure 3.1.15 Bus Collision Detection Control Register ......................................................... 3-10 Figure 3.1.16 Watchdog Timer H .............................................................................................. 3-11 Figure 3.1.17 Timer X ................................................................................................................. 3-12 Figure 3.1.18 Timer Y ................................................................................................................. 3-13 Figure 3.1.19 Timer 1 ................................................................................................................. 3-13 Figure 3.1.20 Timer 2 ................................................................................................................. 3-14 Figure 3.1.21 Timer X Mode Register ...................................................................................... 3-14 Figure 3.1.22 Timer Y Mode Register ...................................................................................... 3-15 Figure 3.1.23 Timer XY Control Register ................................................................................. 3-15 Figure 3.1.24 Timer 1 Mode Register ....................................................................................... 3-16 Figure 3.1.25 Timer 2 Mode Register ....................................................................................... 3-16 Figure 3.1.26 CPU Mode Register ............................................................................................ 3-17 Figure 3.1.27 Interrupt Request Register 1 ............................................................................. 3-18 Figure 3.1.28 Interrupt Request Register 2 ............................................................................. 3-18 Figure 3.1.29 Interrupt Control Register 1 ............................................................................... 3-19 Figure 3.1.30 Interrupt Control Register 2 ............................................................................... 3-19 Figure 3.8.1 SFR Memory Map ................................................................................................. 3-65 Figure 3.9.1 Pinout of 7480 Group (top view) ......................................................................... 3-66 Figure 3.9.2 Pinout of 7481 Group (top view) ......................................................................... 3-67 |
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