7480 datasheet(99/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

1-82

1.12 Timer X and Timer Y

HARDWARE

(2)

Setting of Programmable Waveform Generation Mode

Figures 1.12.19 and 1.12.20 show the setting of the programmable waveform generation mode.

Figure 1.12.19 Setting of Programmable Waveform Generation Mode (1)

Timer X count stop (when timer X is used)

Timer Y count stop (when timer Y is used)

Procedure 1 Stop of timer count

Timer XY control register (TXYCON) [Address 00F816]

Programmable waveform generation mode (Note 3)

Timer X write control

0: Writing to latch and timer simultaneously

1: Writing to only latch

Procedure 3 Setting timer mode register

Timer X mode register (TXM) [Address 00F616]

• when timer X is used

Timer X count source selection

00: f(XIN)/2

01: f(XIN)/8

10: f(XIN)/16

11: Not available

: ‘Not implemented’.

Notes 1: Pay attention to the output level of CNTR pin.

2: In the 7480 Group, these bits are not implemented.

Port P40 output mode (when timer X is used)

Port P41 output mode (when timer Y is used)

Port P4 direction register (P4D) [Address 00C916]

Procedure 2 Setting INT pin input and CNTR pin output

1. Setting port pin which has the alternative function of the CNTR pin to output mode (Note 1)

INT0 edge polarity selection (when timer X is used)

Edge polarity selection register (EG) [Address 00D416]

2. Setting INT edge selection bit when timer is activated by the trigger of INT pin input

(Note 2)

Notes 3: The CNTR pin output is initialized to LOW when the operation mode

bits set to other modes are set to the programmable waveform

generation mode.

INT1 edge polarity selection (when timer Y is used)

0: Timer is activated by detecting the falling edge of INT pin input

1: Timer is activated by detecting the rising edge of INT pin input

Output level latch

Timer X trigger selection

0: Timer X free run

1: Trigger occurrence (input signal of INT0 pin) and timer X start

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