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7480 Datasheet(PDF) 103 Page - Renesas Technology Corp |
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7480 Datasheet(HTML) 103 Page - Renesas Technology Corp |
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103 / 337 page ![]() 7480 Group and 7481 Group User's Manual 1-86 1.12 Timer X and Timer Y HARDWARE (2) Setting of Programmable One-Shot Output Mode Figures 1.12.22 and 1.12.23 show the setting of the programmable one-shot output mode. Figure 1.12.22 Setting of Programmable One-Shot Output Mode (1) Timer X count stop (when timer X is used) Timer Y count stop (when timer Y is used) Procedure 1 Stop of timer count Timer XY control register (TXYCON) [Address 00F816] b7 b0 11 Programmable one-shot output mode (Note 3) Timer X write control 0: Writing to latch and timer simultaneously 1: Writing to only latch Procedure 3 Setting timer mode register Timer X mode register (TXM) [Address 00F616] b7 b0 • when timer X is used Timer X count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available 1 0 1 b2 b3 : ‘Not implemented’. Notes 1: Pay attention to the output level of CNTR pin. 2: In the 7480 Group, these bits are not implemented. Port P40 output mode (when timer X is used) Port P41 output mode (when timer Y is used) Port P4 direction register (P4D) [Address 00C916] b7 b0 Procedure 2 Setting INT pin input and CNTR pin output 1. Setting port pin which has the alternative function of the CNTR pin to output mode (Note 1) INT0 edge polarity selection (when timer X is used) Edge polarity selection register (EG) [Address 00D416] b7 b0 2. Setting INT edge selection bit and CNTR edge selection bit 1 (Note 2) 1 Notes 3: When setting operation mode, CNTR pin output is initialized to the contents of the CNTR edge selection bit. INT1 edge polarity selection (when timer Y is used) 0: Falling edge of INT pin input detected 1: Rising edge of INT pin input detected CNTR0 edge polarity selection (when timer X is used) CNTR1 edge polarity selection (when timer Y is used) 0: HIGH level from CNTR pin is output after the maximum 1 cycle of count source from trigger detection of INT pin input. 1: LOW level from CNTR pin is output after the maximum 1 cycle of count source from trigger detection of INT pin input. |
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