7480 datasheet(79/337 Pages) RENESAS

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1-62

1.12 Timer X and Timer Y

HARDWARE

7480 Group and 7481 Group User's Manual

(2)

Timer X Mode Register, Timer Y Mode Register, and Timer XY Control Register

These registers consist of the bits controlling the operations of timer X and timer Y.

Figures 1.12.5, 1.12.6, and 1.12.7 show the timer X mode register, timer Y mode register, and timer

XY control register respectively.

Figure 1.12.5 Timer X Mode Register

Timer X mode register

b4 b3 b2 b1 b0

Name

Function

At reset

Timer X mode register (TXM) [Address 00F616]

Timer X operating mode bits

b2 b1 b0

Timer X write control bit

Output level latch

Timer X trigger selection bit

0 : Writing to both latch and timer

1 : Writing to latch only

Timer X count source

selection bits

0 : Timer X free run in programmable

waveform generation mode

1 : Trigger occurrence (input signal of INT0

pin) and timer X start in programmable

waveform generation mode

b7 b6

0 0 : f(XIN)/2

0 1 : f(XIN)/8

1 0 : f(XIN)/16

1 1 : Input from CNTR0 pin

0 : LOW output from CNTR0 pin

1 : HIGH output from CNTR0 pin

0 0 0 : Timer • event count mode

0 0 1 : Pulse output mode

0 1 0 : Pulse period measurement mode

0 1 1 : Pulse width measurement mode

1 0 0 : Programmable waveform

generation mode

1 0 1 : Programmable one-shot output

mode

1 1 0 : PWM mode

1 1 1 : Not available

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