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7480 Datasheet(PDF) 84 Page - Renesas Technology Corp |
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7480 Datasheet(HTML) 84 Page - Renesas Technology Corp |
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84 / 337 page ![]() 1-67 1.12 Timer X and Timer Y HARDWARE 7480 Group and 7481 Group User's Manual Figure 1.12.8 Operation Example in Timer Mode and Event Count Mode RL RL RL Count source (Note 2) 000016 TL Timer X stop control bit Timer X interrupt request bit ‘0’ is written ‘0’ is written ‘1’ is written Writing to timer X (Note 1) Time Count start Count stop T Count start 1 5 2 A A A 3 6 UF UF UF 4 Notes 1: In this case, timer X write control bit is ‘0’ (writing to timer and timer latch simultaneously). 2: In event count mode, • when CNTR edge selection bit is ‘0’, CNTR pin input is used as the count source. • when CNTR edge selection bit is ‘1’, the inverted CNTR pin input is used as the count source. TL RL UF T : Setting value to timer X : Contents of timer latch is reloaded : Underflow : Count period A : Clearing by writing ‘0’ to interrupt request bit or accepting interrupt request T(s) = 1 Count source frequency × (Setting value to timer X + 1) |
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