7480 datasheet(71/337 Pages) RENESAS

71 / 337 page

7480 Group and 7481 Group User's Manual

1-54

HARDWARE

1.11 Interrupts

1.11.6 Setting of Interrupts

Figures 1.11.12 and 1.11.13 show the setting of interrupts.

Figure 1.11.12 Setting of Interrupts (1)

Interrupt disabled

Procedure 1 Setting interrupt disable flag to ‘1’ to disable the acceptance of other interrupts during setting.

Processor status register (PS)

When timer X interrupt is set, timer X interrupt is disabled.

Procedure 2 Setting using interrupt enable bit to ‘0’ (disabled)

Interrupt control register 1 (ICON1) [Address 00FE16]

Interrupt control register 2 (ICON2) [Address 00FF16]

When timer Y interrupt is set, timer Y interrupt is disabled.

When timer 1 interrupt is set, timer 1 interrupt is disabled.

When timer 2 interrupt is set, timer 2 interrupt is disabled.

When serial I/O receive interrupt is set, serial I/O receive interrupt is disabled.

When serial I/O transmit interrupt is set, serial I/O transmit interrupt is disabled.

When bus arbitration interrupt is set, bus arbitration interrupt is disabled.

When A-D conversion completion interrupt is set, A-D conversion completion interrupt is disabled.

When INT0 interrupt is set, INT0 interrupt is disabled.

When INT1 interrupt is set, INT1 interrupt is disabled.

When CNTR0 interrupt is set, CNTR0 interrupt is disabled.

When CNTR1 interrupt is set, CNTR1 interrupt is disabled.

2. When CNTR interrupt and key-on wakeup interrupt are used, using port is set to input mode.

3. When key-on wakeup interrupt is used, using port pins are pulled high.

Procedure 3 Setting each interrupt

Edge polarity selection register (EG) [Address 00D416]

INT0 edge polarity selection

INT1 edge polarity selection

CNTR0 edge polarity selection

CNTR1 edge polarity selection

INT1 source at STP and WIT selection

0 : P31/INT1

1 : P00–P07 LOW level (Key-on wakeup)

0: Falling edge

1: Rising edge

• When INT interrupt, CNTR interrupt and key-on wakeup interrupt are used

1. Selection of edge polarity selection register

• When timer interrupt is used

1. Stop of timer count

2. Setting of each mode

3. Setting of timer (except pulse period measurement mode and pulse width measurement mode)

• When serial I/O receive interrupt, serial I/O transmit interrupt or bus arbitration interrupt are used

1. Setting of registers related to serial I/O

2. Setting of baud rate generator (only when internal clock is selected as synchronous clock)

Note: For details, refer to setting of each function.

7480 Datasheet(PDF) 71 Page - Renesas Technology Corp

7480 Datasheet(HTML) 71 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL