7480 datasheet(102/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

1-85

1.12 Timer X and Timer Y

HARDWARE

When the timer X or Y operation mode bits of the timer X or Y mode register are set to the

programmable one-shot output mode, the CNTR pin outputs are initialized to the content of the CNTR

edge selection bit ( in Figure 1.12.21).

The CNTR pin output remains at the inverted level of the content of the CNTR edge selection bit for

the period from the rising edge∗1 of the count source immediately after the valid edge of an INT pin

input is detected until the subsequent an underflow ( in Figure 1.12.21).

Notes 1: Keep the trigger widths input to the INT pins 250 ns or more.

2: In the programmable one-shot output mode, the output level of a CNTR pin is inverted

when the CNTR edge selection bit is switched ( in Figure 1.12.21).

∗1: One cycle or less of the rising edge of the count source, after the valid edge of an INT pin input

is detected.

Figure 1.12.21 Operation Example in Programmable One-Shot Output Mode

Count source

000016

Timer X stop control bit

INT0 pin input

(Note 2)

‘0’ is

written

Time

Count start

Timer X interrupt request bit

INT0

interrupt request bit

CNTR0 pin output

Writing to timer X

(Note 1)

Initialized to the contents of CNTR0 edge selection bit

when setting timer X operation mode bits

Notes 1: In this case, timer X write control bit is ‘0’ (writing to timer and timer latch simultaneously).

2: In this case, INT0 edge selection bit is ‘1’ (rising edge is valid).

: Setting value to timer X

: Contents of timer latch is reloaded

: Underflow

: Pulse width

: Clearing by writing ‘0’ to interrupt request bit or accepting interrupt request

H(s) =

Count source frequency × (Setting value to timer X + 1)

CNTR0

edge selection bit

‘0’ is

written

Undefined

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