TMS370 datasheet(60/73 Pages) TI

60 / 73 page

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external clocking requirements for clock divided by 4† (see Figure 24)

NO.

PARAMETER

MIN

MAX

UNIT

tw(Cl)

Pulse duration, XTAL2/CLKIN (see Note 12)

tr(Cl)

Rise time, XTAL2/CLKIN

tf(CI)

Fall time, XTAL2/CLKIN

td(CIH-SCL)

Delay time, XTAL2/CLKIN rise to SYSCLK fall

100

CLKIN§

Crystal operating frequency

MHz

SYSCLK¶

System clock‡

0.5

MHz

† For VIL and VIH, refer to recommended operating conditions table.

‡ SYSCLK = CLKIN/4

§ ’x69A operates up to 12 MHz CLKIN

¶ ’x69A operates up to 3 MHz SYSCLK

NOTE 12: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

SYSCLK

Figure 24. External Clock Divide-by-4

external clocking requirements for clock divided by 1 (PLL)† (see Figure 25)

NO.

PARAMETER

MIN

MAX

UNIT

tw(Cl)

Pulse duration, XTAL2/CLKIN (see Note 12)

tr(Cl)

Rise time, XTAL2/CLKIN

tf(CI)

Fall time, XTAL2/CLKIN

td(CIH-SCH)

Delay time, XTAL2/CLKIN rise to SYSCLK rise

100

CLKIN#

Crystal operating frequency

MHz

SYSCLK¶

System clock||

MHz

† For VIL and VIH, refer to recommended operating conditions table.

¶ ’x69A operates up to 3 MHz SYSCLK

# ’x69A operates up to 3 MHz CLKIN (for divide-by-1 clock option)

|| SYSCLK = CLKIN/1

NOTE 12: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

SYSCLK

Figure 25. External Clock Divide-by-1

TMS370 Datasheet(PDF) 60 Page - Texas Instruments

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