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TMS370 Datasheet(PDF) 33 Page - Texas Instruments |
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TMS370 Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 73 page  TMS370Cx6x 8-BIT MICROCONTROLLER SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 33 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timer 2n modules (T2A and T2B) (continued) D Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input-capture pins (T2nIC1/CR) D Interrupts that can be generated on the occurrence of: – A compare equal for dedicated-compare register – A compare equal for capture-compare register – A counter overflow – An external edge 1 detection – An external edge 2 detection D Fourteen control registers for each Timer 2 module: Located in the PF frame beginning at address P060 and P080 for T2A and T2B, respectively. The timer 2n module control registers are illustrated in Table 18. Table 18. Timer 2n Module Register Memory Map PF PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG Modes: Dual-Compare and Dual-Capture P060 P080 Bit 15 T2n Counter MSbyte Bit 8 T2nCNTR P061 P081 Bit 7 T2n Counter LSbyte Bit 0 T2nCNTR P062 P082 Bit 15 Compare Register MSbyte Bit 8 T2nC P063 P083 Bit 7 Compare Register LSbyte Bit 0 T2nC P064 P084 Bit 15 Capture/Compare Register MSbyte Bit 8 T2nCC P065 P085 Bit 7 Capture/Compare Register LSbyte Bit 0 T2nCC P066 P086 Bit 15 Capture Register 2 MSbyte Bit 8 T2nIC P067 P087 Bit 7 Capture Register 2 LSbyte Bit 0 T2nIC P06A P08A — — — T2n OVRFL INT ENA T2n OVRFL INT FLAG T2n INPUT SELECT1 T2n INPUT SELECT0 T2n SW RESET T2nCTL1 Mode: Dual-Compare P06B P08B T2nEDGE1 INT FLAG T2nC2 INT FLAG T2nC1 INT FLAG — — T2nEDGE1 INT ENA T2nC2 INT ENA T2nC1 INT ENA T2nCTL2 P06C P08C T2n MODE = 0 T2nC1 OUT ENA T2nC2 OUT ENA T2nC1 RST ENA T2nEDGE1 OUT ENA T2nEDGE1 POLARITY T2nEDGE1 RST ENA T2nEDGE1 DET ENA T2nCTL3 Mode: Dual-Capture P06B P08B T2nEDGE1 INT FLAG T2nEDGE2 INT FLAG T2nC1 INT FLAG — — T2nEDGE1 INT ENA T2nEDGE2 INT ENA T2nC1 INT ENA T2nCTL2 P06C P08C T2n MODE = 1 — — T2nC1 RST ENA T2nEDGE2 POLARITY T2nEDGE1 POLARITY T2nEDGE2 DET ENA T2nEDGE1 DET ENA T2nCTL3 Modes: Dual-Compare and Dual-Capture P06D P08D — — — — T2nEVT DATA IN T2nEVT DATA OUT T2nEVT FUNCTION T2nEVT DATA DIR T2nPC1 P06E P08E T2nIC2 / PWM DATA IN T2nIC2 / PWM DATA OUT T2nIC2 / PWM FUNCTION T2nIC2 / PWM DATA DIR T2nIC1/CR DATA IN T2nIC1/CR DATA OUT T2nIC1/CR FUNCTION T2nIC1/CR DATA DIR T2nPC2 P06F P08F T2n STEST T2n PRIORITY — — — — — — T2nPRI |
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