TMS370 datasheet(35/73 Pages) TI

35 / 73 page

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

timer 2n modules (T2A and T2B) (continued)

The timer 2n dual-capture mode block diagram is illustrated in Figure 13. The annotations on the diagram

identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2nCTL2.0 is

106Bh (n = A) or 108Bh (n = B), bit 0, in the T2nCTL2 register.

T2nCTL2.5

T2nCTL3.3

Capt/Comp

T2nPC2.3–0

Compare =

Clock

Source

16-Bit

Counter

MSB

LSB

T2nCNTR.15–0

Reset

T2nC1

RST ENA

T2n SW

RESET

T2nCTL1.0

T2nCTL3.4

T2nCTL2.6

T2nCTL2.1

T2nCTL2.7

T2nCTL2.2

T2nCTL2.0

16-Bit

MSB

LSB

T2nC.15–0

16-Bit

Compare

MSB

LSB

T2n PRIORITY

Level 1 Int

Level 2 Int

T2nCTL1.3

T2nCTL1.4

16-Bit

Capture

MSB

LSB

T2nIC.15–0

Edge 2

Select

T2nIC2/PWM

T2nPC2.7–4

T2nCTL3.1

Edge1

Select

T2nIC1/CR

T2nCTL3.2

T2nCTL3.0

T2nEDGE1 POLARITY

T2nEDGE1 DET ENA

T2nEDGE2 DET ENA

T2nEDGE2 POLARITY

T2nC1 INT FLAG

T2nC1 INT ENA

T2n OVRFL INT FLAG

T2n OVRFL INT ENA

T2nEDGE1 INT FLAG

T2nEDGE1 INT ENA

T2nEDGE2 INT ENA

T2nEDGE2 INT FLAG

T2nPRI.6

T2nCC.15 – 0

Figure 13. Dual-Capture Mode

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