TMS370 datasheet(8/73 Pages) TI

8 / 73 page

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory/peripheral wait operation

The TMS370Cx6x enhances interface flexibility by providing WAIT-state support, decoupling the cycle time of

the CPU from the read/write access of the external memory or peripherals. External devices can extend the

read/write accesses indefinitely by placing an active low on the WAIT input pin. The CPU continues to wait as

long as WAIT remains active.

Programmable automatic wait-state generation also is provided by the TMS370Cx6x on-chip bus controller.

Following a hardware reset, the TMS370Cx6x is configured to add one wait state to all external bus transactions

and memory and peripheral accesses, thus making every external access a minimum of three system clock

cycles. The designer can disable the automatic wait-state generation if the AUTOWAIT DISABLE bit in SCCR1

is set to 1. Also, all accesses to the upper four frames of the peripheral file can be extended independently to

four system clock cycles if the PF AUTO WAIT bit in SCCR0 is set to one. Programmable wait states can be

used in conjunction with the external WAIT pin. In applications where the external device read/write access can

interface with the TMS370Cx6x CPU using one wait state, the automatic wait-state generation can eliminate

external WAIT interface logic, lowering system cost.

TMS370 Datasheet(PDF) 8 Page - Texas Instruments