TMS370 datasheet(29/73 Pages) TI

29 / 73 page

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

The TMS370Cx6x device includes a 24-bit watchdog (WD) timer, contained in the T1 module, which can be

software programmed as an event counter, pulse accumulator, or interval timer if the watchdog function is not

desired. The WD function is to monitor software and hardware operation and to implement a system reset when

the WD counter is not serviced properly (WD counter overflow or WD counter is reinitialized by an incorrect

value). The WD can be configured as one of three mask options: standard watchdog, hard watchdog, or simple

counter.

D Standard watchdog configuration (see Figure 8) – for ’76xA EPROM and mask-ROM devices

–

Watchdog mode

–

Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK

–

A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

–

Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

–

A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

–

Non-watchdog mode

–

Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer.

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

WD OVRFL

RST ENA

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.7

T1CTL2.5

WD OVRFL

Interrupt

T1CTL2.6

WD OVRFL

INT FLAG

Figure 8. Standard Watchdog

TMS370 Datasheet(PDF) 29 Page - Texas Instruments

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