TMS370 datasheet(67/73 Pages) TI

67 / 73 page

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SPI-master mode external timing characteristics and requirements (see Note 14 and Figure 31)

NO.

MIN

MAX

UNIT

tc(SPC)M

Cycle time, SPICLK

2tc

256tc

tw(SPCL)M

Pulse duration, SPICLK low

tc – 45

0.5tc(SPC)+45

tw(SPCH)M

Pulse duration, SPICLK high

tc – 55

0.5tc(SPC)+45

td(SPCL-SIMOV)M

Delay time, SPISIMO valid after SPICLK low (polarity = 1)

– 65

tv(SPCH-SIMO)M

Valid time, SPISIMO data valid after SPICLK high

(polarity =1)

tw(SPCH) – 50

tsu(SOMI-SPCH)M

Setup time, SPISOMI to SPICLK high (polarity = 1)

0.25 tc + 150

tv(SPCH-SOMI)M

Valid time, SPISOMI data valid after SPICLK high

(polarity = 1)

NOTE 14: tc = system-clock cycle time = 1 / SYSCLK

Data Valid

SPISOMI

SPISIMO

SPICLK

NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0.

Figure 31. SPI-Master External Timing

TMS370 Datasheet(PDF) 67 Page - Texas Instruments

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