TMS370 datasheet(19/73 Pages) TI

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TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

interrupts (continued)

Table 11. Hardware-System Interrupts

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM

INTERRUPT

VECTOR

ADDRESS

PRIORITY†

External RESET

Watchdog overflow

Oscillator fault detect

COLD START

WD OVRFL INT FLAG

OSC FLT FLAG

RESET‡

7FFEh, 7FFFh

External INT1

INT1 FLAG

INT1‡

7FFCh, 7FFDh

External INT2

INT2 FLAG

INT2‡

7FFAh, 7FFBh

External INT3

INT3 FLAG

INT3‡

7FF8h, 7FF9h

SPI RX/TX complete

SPI INT FLAG

SPIINT

7FF6h, 7FF7h

Timer 1 overflow

Timer 1 compare 1

Timer 1 compare 2

Timer 1 external edge

Timer 1 input capture 1

Watchdog overflow

T1 OVRFL INT FLAG

T1C1 INT FLAG

T1C2 INT FLAG

T1EDGE INT FLAG

T1IC1 INT FLAG

WD OVRFL INT FLAG

T1INT§

7FF4h, 7FF5h

SCI RX data register full

SCI RX break detect

RXRDY FLAG

BRKDT FLAG

RXINT‡

7FF2h,7FF3h

SCI TX data register empty

TXRDY FLAG

TXINT

7FF0h, 7FF1h

Timer 2A overflow

Timer 2A compare 1

Timer 2A compare 2

Timer 2A external edge

Timer 2A input capture 1

Timer 2A input capture 2

T2A OVRFL INT FLAG

T2AC1 INT FLAG

T2AC2 INT FLAG

T2AEDGE INT FLAG

T2AIC1 INT FLAG

T2AIC2 INT FLAG

T2AINT

7FEEh, 7FEFh

ADC1 conversion complete

AD INT FLAG

ADINT

7FECh, 7FEDh

Timer 2B overflow

Timer 2B compare 1

Timer 2B compare 2

Timer 2B external edge

Timer 2B input capture 1

Timer 2B input capture 2

T2B OVRFL INT FLAG

T2BC1 INT FLAG

T2BC2 INT FLAG

T2BEDGE INT FLAG

T2BIC1 INT FLAG

T2BIC2 INT FLAG

T2BINT

7FBEh, 7FBFh

† Relative priority within an interrupt level

‡ Release microcontroller from STANDBY and HALT low-power modes

§ Release microcontroller from STANDBY low-power mode

privileged operation and EEPROM write-protection override

The TMS370Cx6x family has significant flexibility to enable the designer to software-configure the system and

peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation

ensures the integrity of the system configuration, once it is defined for an application. Following a hardware

reset, the TMS370Cx6x operates in the privileged mode, where all peripheral file registers have unrestricted

read/write access, and the application program configures the system during the initialization sequence

following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set

to 1 to enter the nonprivileged mode, disabling write operations to specific configuration control bits within the

peripheral file. Table 12 lists the system configuration bits that are write-protected during the nonprivileged

mode and must be configured by software prior to exiting the privileged mode.

TMS370 Datasheet(PDF) 19 Page - Texas Instruments

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